This field of this invention relates generally to the non-destructive testing of integrated circuits (IC's) in the electronics industry, and relates more particularly to high speed accurate testing of IC's using generally planar membrane test probe cards.
Non-destructive methods now exist for testing integrated circuits. Integrated circuits are generally grown or formed layer by layer as a plurality of semiconductor chips having input/output pads in large batches on thin planar substrates called wafers. Before the wafer is cut into individual chips, the circuits on each chip must be inspected and checked.
This testing operation is usually performed while the circuits still reside together on a single wafer, since testing after the dies have been sawn apart and packaged is prohibitively expensive. Hundreds of separate devices on every wafer are analyzed by passing input signals from a test probe, a planar test membrane or a planar membrane test card, into each device and monitoring voltage levels at selected output locations on the tiny circuits.
Each chip has test pads designed to electrically make contact with other devices. Because of height differences in these pads, conventional probe devices often make erroneous contact and thus produce inaccurate results. Large geometric and height discrepancies among these surface features cause faulty electrical connections between the test probe and the input/output pads of the device under test (DUT).
Specifically, the support structure carrying the test membranes cannot compensate for misalignment between the plane of the test probe membrane and the DUT. Because the test membrane cannot be aligned to be coplanar with the wafer bearing the many chips, the art of chip testing routinely experiences testing errors that preferably should be eliminated.
Because of this plane alignment problem, testers have had difficulty performing uniformly reliable tests at high speed with minimal test inaccuracy caused by irregularities in test pad height.
To solve these and other problems, the present invention offers method and apparatus for providing an automatic self-leveling action for a membrane probe card or membrane. The invention is used for providing high speed test signals to an integrated circuit array residing on a wafer.
This innovative technique enhances the performance of previous membrane probe card designs by reducing the incidence of inaccurate test results that are caused by the failure of the probe contacts to make a complete electrical coupling to the input/output pads of a device under test.